SPNDEN=0, CPHA=0, SPB=others, SCKDEN=0, SSLA=000, BRDV=00, SLNDEN=0, LSBF=0, CPOL=0
SPI Command Register 0
| CPHA | RSPCK Phase Setting 0 (0): Data sampling on odd edge, data variation on even edge 1 (1): Data variation on odd edge, data sampling on even edge |
| CPOL | RSPCK Polarity Setting 0 (0): RSPCK is low when idle 1 (1): RSPCK is high when idle |
| BRDV | Bit Rate Division Setting 0 (00): These bits select the base bit rate 1 (01): These bits select the base bit rate divided by 2 2 (10): These bits select the base bit rate divided by 4 3 (11): These bits select the base bit rate divided by 8 |
| SSLA | SSL Signal Assertion Setting 0 (others): Setting prohibited 0 (000): SSL0 1 (001): SSL1 2 (010): SSL2 3 (011): SSL3 |
| Reserved | This bit is read as 0. The write value should be 0. |
| SPB | SPI Data Length Setting 0 (others): Setting prohibited 4 (0100): 8 bits 5 (0101): 8 bits 6 (0110): 8 bits 7 (0111): 8 bits 8 (1000): 9 bits 9 (1001): 10 bits 10 (1010): 11 bits 11 (1011): 12 bits 12 (1100): 13 bits 13 (1101): 14 bits 14 (1110): 15 bits 15 (1111): 16 bits |
| LSBF | SPI LSB First 0 (0): MSB first 1 (1): LSB first |
| SPNDEN | SPI Next-Access Delay Enable 0 (0): A next-access delay of 1 RSPCK + 2 PCLK 1 (1): A next-access delay is equal to the setting of the SPI next-access delay register (SPND) |
| SLNDEN | SSL Negation Delay Setting Enable 0 (0): An SSL negation delay of 1 RSPCK 1 (1): An SSL negation delay is equal to the setting of the SPI slave select negation delay register (SSLND) |
| SCKDEN | RSPCK Delay Setting Enable 0 (0): An RSPCK delay of 1 RSPCK 1 (1): An RSPCK delay is equal to the setting of the SPI clock delay register (SPCKD) |